one thing that slightly grates me about RISC-V is how it encodes intermediates and addresses split over multiple instructions

I understand why it is—simplicity of hardware implementation—but say,

auipc t3,0x19
ld t3,1888(t3) # 1d400 <strlen@GLIBC_2.27>
jalr t1,t3

to jump to a (far) address takes some getting used to, and means relocations need to fix up at two locations

…or that

li a0, 0xcafebabe

gets assembled as

lui a0,0x32
addi a0,a0,-1029
slli a0,a0,0xe
addi a0,a0,-1346

for a total of 16 bytes


(though, in practice this is avoided by doing a relative load instead of using immediate encoding)

Sign in to participate in the conversation
unidentified instance

swarm ops (instance image by мøтħer ¢røω)