@FreePietje wow that's … a really cool and unexpected development


"A 100% libre RISC-V + 3D GPU chip for mobile devices"

"The application for funding from NLnet and the Next Generation Internet initiative from the European Commission, from back in November of last year, has been approved. It means that we have EUR 50,000 to pay for full-time engineering work to be carried out over the next year, and to pay for bounty-style tasks. For the right people, with the right skills, there is money now available."


cc @orionwl

@emilengler haah there's already a command that will do that:

socat TCP:<ip>:<port> SYSTEM:'stty rows 30 cols 40 && '"$*",pty,setsid,ctty,stderr

the advantage of that (to piping) is that it'll recognize a pty (so use colors and stuff automatically), as well as allows to set the terminal size

40×30 chars is not a lot but it still works to keep track of e.g. builds in process, just pipe anything to nc at the appropriate ip/port

@FreePietje even with the bootloader layers all the way down it's not nearly as bad as UEFI's hellish complexity though 😂 and at least for SiFive it's all open source

@FreePietje you're right, thinking of it, i forgot a stage; there's the ZSBL (zero-stage boot loader) in boot ROM, then FSBL (first-stage boot loader).

BBL is after that (it's part of the kernel image currently), and will be replaced by opensbi + u-boot.

@FreePietje so this opensbi and u-boot go into the boot chain, making it quite complex; currently it's (for SiFive)

boot ROM→BBL→kernel

it becomes

boot ROM→BBL→opensbi→u-boot→kernel

(this to facilitate virtualization and emulation and such), e.g. on qemu SBI can communicate with the host instead of hardware, and u-boot allows for selecting kernels in a boot menu

but i'm still using the old stack right now, just upgraded to kernel 5.1.0 final

@jon oh wow that's *awesome* news. completely agree with her conclusion on RISC-V versus POWER9 for user-facing devices

but it's for longer term: RISC-V is moving quickly but wouldn't hold my breath for miniaturized, complex, fully integrated, high-performance device like a laptop (see the bulk of the SiFive Unleashed RISC-V computer) any time soon, but who knows?

@waxwing @jon kinda want one now, my current ASUS is horse shit 😥

what has kept me back from Librem is that they're Intel (have been avoiding that), as well as fairly expensive, but open-source-as-much-as-possible —from coreboot down—is good and might just go with that for now

also been looking forward to PINEBOOK Pro but it's a very different performance class

what's your experience with Purism? is it stable? does it feel solid? can you easily open it when necessary (e.g. to clean out dust)?

@FreePietje thanks for the info ! opensbi/u-boot work is promising

haven't really been keeping track of debian risc-v, still fedora here 🙂 should probably join OFTC some time

@orionwl there is now a u-boot-sifive package in Debian experimental and also 'opensbi' (RISC-V Open Source Supervisor Binary Interface).

Maintainer of opensbi and u-boot also did a presentation wrt RISC-V in Debian: archive.org/details/latch_2019

There is now also a section "Setting up a riscv64 virtual machine with u-boot and opensbi" added on wiki.debian.org/RISC-V (and some other updates)

There's also reasonable activity on -riscv (OFTC)

@flexbit i don't really know anything about the details of font handling in X etc, was surprised it worked for me 😅

@jamieasefa it's … a very interesting specimen of weird Chinese tech … it's a full RISCV-GC SoC for cheap, but missing a MMU (though some people managed to boot MMU-less Linux on it, it rules out some uses for security)
it's pretty cool that it comes with a camera and touch display though, and the KPU neural network accelerator is interesting too (a bit specific and creepy tho, too, given the context)

just created a repository with a Kendryte K210 SoC memory map (reverse-engineered from various sources) and additional demos:
- the glyph mapping one that I posted a video of
- and an OTP dumper tool


I intend to add some more in the future as time allows

@emilengler FWIW i definitely didn't write the above code
but i don't think '&&' or '||' is a thing in python, there's '&' for bitwise AND, 'and' for logical AND, '|' for bitwise OR, and 'or' for logical OR

"dinosaur infested" must be the best metaphor for dangerously tricky code that I've ever seen

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